1. Field of the Invention
The present invention relates generally to an algorithmic analog-to-digital converter. More particularly, the present invention relates to an algorithmic analog-to-digital converter having digital code redundancy and digital self-calibration for calibration of gain and reduction of offset, differential non-linearity and integral non-linearity.
2. Description of the Background Art
Analog-to-digital converters are in widespread use for interfacing analog signals to digital computers, and for digital signal processing of analog signals. There are various types of analog-to-digital converters, each having different cost and performance characteristics. The cost is dictated by circuit complexity and the technology needed to implement the circuit components. The performance characteristics are typically measured in terms of conversion speed, resolution, offset, differential non-linearity, integral non-linearity, and power consumption.
For many applications, analog-to-digital converters can be fabricated in analog complementary metal-oxide semiconductor (CMOS) technology to meet desired performance characteristics at low cost. Delta-sigma converters, successive approximation converters, and algorithmic converters have all been fabricated in CMOS technology, and each provides a particular combination of desired characteristics that could be best for a specific application. Delta-sigma (.DELTA.-.SIGMA.) converters provide the best performance and have a relatively small size on a CMOS integrated circuit chip, but delta-sigma converters have a relatively high power consumption. Successive approximation (SAR) converters provide the lowest power consumption but have a relatively large size. Algorithmic converters have low power consumption and small size.
An algorithmic converter typically uses a cyclic conversion procedure based on the conventional restoring (CR) numerical division principle. In the CR cyclic conversion procedure the signal to be converted is multiplied by two and the product is compared to a reference voltage: if the product is greater than the reference, then the most significant bit (MSB) of the output code is set to 1, and the reference is subtracted from the product; else the MSB is set to 0, and no subtraction is carried out. The remaining part of the product is the so-called "residue voltage" which corresponds to a partial remainder. The residue voltage undergoes the same multiply-by-two, comparison, and conditional subtraction operations to determine the next bit of the output code. The process is repeated to determine the remaining bits of the output code until the least significant bit (LSB) is obtained.
Algorithmic converters have required a precise multiplication-by-2 factor to obtain conversion linearity. For example, Armstrong et al. U.S. Pat. No. 5,027,116 issued Jun. 25, 1991, incorporated herein by reference, discloses a self-calibrating algorithmic analog-to-digital converter for which the gain of the conversion loop is precisely adjusted and controlled by an array of switched capacitors. The control for the switched capacitors is stored in a latch. The offset of the gain stage is reduced by reducing the amount of charge injected from the gate of the input zeroing MOS switch. Further details of such a self-calibrating algorithmic converter are disclosed in Ohara et al., "A CMOS Programmable Self-Calibrating 13-bit Eight-Channel Data Acquisition Peripheral," IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 6, Dec. 1987, pp. 930-938, incorporated herein by reference.
Algorithmic converters are also known to suffer differential and integral nonlinearities unless the loop offset error is reduced to at least 1/2 LSB. The nonlinearities occur because excess offset causes the residue voltage to fall outside of the convergence domain. The nonlinearities can be avoided by using a redundant signed digit (RSD) procedure, in which only a global shift of the transfer characteristic is experienced in the presence of a loop offset error. As described in Ginetti et al., "A CMOS 13-b Cyclic RSD A/D Converter," IEEE Journal of Solid-State Circuits, Vol. 27, No. 7, Jul. 1992, pp. 957-965, incorporated herein by reference, the RSD procedure is similar to the CR cyclic conversion procedure, but at each bit decision, two comparison levels P and Q are used instead of one, with P positive and Q negative: if the product is greater than P, the output code bit is set to 1 and the reference is subtracted; if the product is less than Q, the bit is set to -1 and the reference is added; else, the bit is set to 0 and no addition or subtraction is performed. In addition to the extra comparator, the RSD converter requires a kind of adder circuit to convert the redundant code to a conventional binary representation. The RSD converter still requires a precise gain of 2 for the multiplication of the remainder, although it is said to provide one more bit of differential linearity than the cyclic conversion algorithm. To ensure a precise gain of 2, Ginetti et al. disclose a capacitor mismatch error cancellation technique that involves interchanging two capacitor pairs without using any extra clock phase and without using any extra hardware.
Although the RSD technique appears satisfactory for conversion at the 13-bit level, the RSD technique introduces an additional source of non-linearity not present in the CR cyclic conversion procedure. Because the RSD technique involves adjustment of the residue by three possible levels of +V.sub.ref, 0, and -V.sub.ref, it is necessary for these three levels to lie precisely on a straight line (within the resolution of the conversion) or else non-linearities will occur. Moreover, the Ginetti et al. capacitor mismatch error cancellation technique is ineffective for eliminating all sources of gain variation, such as capacitive coupling between amplifier inputs and outputs, which cause the gain to deviate from an exact value of 2.